The present invention relates generally to multiprocessor systems, and more specifically to address translation technique for multiprocessor systems.
Supercomputers are increasingly used for high-speed calculations in many scientific and industrial applications. To meet the high-speed requirement, multi-processing systems have been developed to process multiple jobs and tasks in a parallel mode. In many of such applications, the amount of data to be processed exceeds the capacity of the main memory of the system, and therefore, a technique known as "virtual memory" is usually employed for virtually expanding the storage area of main memory by creating an extended area in a mass storage system such as hard disks. With this technique, logical memory addresses in a program are translated to physical memory addresses on a per page basis using address translation tables stored in the main memory before it is accessed by each processor. To reduce the access time, a high-speed, translation lookaside buffer is provided, and each processor loads its identification number and a copy of the address table into the buffer. As a result, in a multitasking mode, processors load address translation tables into the buffer when they attempt to access the same pages and therefore processor overhead for address mapping increases. One solution to this problem would be the use of a technique by which all address translation tables that correspond to a segmented virtual space are simultaneously loaded as disclosed in U.S. Pat. No. 4,481,573. However, as discussed in this patent, there must be provided as many translation lookaside buffers as there are processors, resulting in an increase in hardware cost.